Power Efficient adder Cell For Low Power Bio MedicalDevices

In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on power consumption, speed and power delay product (PDP). Cadence simulations show that the proposed adder can work more reliably at different range of supply voltage over a frequency of ranges. The Simulations carried out showed that the proposed adder design has 37.3% power savings capability over conventional 28-T CMOS adder at 200 MHz for a supply voltage of 1.1V with negligible area overhead. The proposed design has been used as the basic building block for column compression Dadda multipliers (CCDM) and found to be working successfully with high energy efficiency.